DSL Chip

• Conceptual / specification work
• VHDL design, simulation
• Verification concept development (VHDL interface models, C stimuli generation and comparison software,
• regression environment)
• Integration of various digital and analog Soft- and Hardmacros
• Synthesis
• Scan insertion
• Floorplanning, P&R
• Physical verification
  
  
• Project duration: 7 months
• First time right
• Gate count complexity: 2.8M